Logic synthesis
Synthesis by spectral translation using Boolean decision diagrams
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Digital Systems: Hardware Organization and Design
Digital Systems: Hardware Organization and Design
Minimization of Haar wavelet series and Haar spectral decision diagrams for discrete functions
Computers and Electrical Engineering
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An exclusive-OR transform of input variables significantly reduces the size of the PLA implementation for adder and comparator circuits. For n bit adder circuits, the size of PLA for transformed functions is O(n/sup 2/). In comparison, when the complete truth-table of an adder is minimized, the PLA size will be O(2/sup n+2/). Similarly, for an n bit comparator, the size of the PLA is reduced from O(2/sup n+1/) to O(n). These implementations require additional transform logic of complexity O(n), consisting of exclusive-OR gates.