IEEE Transactions on Computers
Software synthesis from synchronous specifications using logic simulation techniques
Proceedings of the 39th annual Design Automation Conference
Binary Polynomial and Nonlinear Digital Filters
Binary Polynomial and Nonlinear Digital Filters
Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
ISMVL '01 Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic
Finite Orthogonal Series in Design of Digital Devices
Finite Orthogonal Series in Design of Digital Devices
Evaluation of multiple-output logic functions using decision diagrams
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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In this paper, a minimization of Haar wavelet series for simplification of circuits and Haar based decision diagrams representing discrete multiple-valued functions is proposed. The minimization is performed by permutation of indices of generalized Haar functions. Experimental results show that this method provides reasonable reduction in the number of non-zero coefficients. The Haar series reduced this way can be useful in the circuit synthesis for realization of multiple-valued functions. The same algorithm can be also used to reduce the number of paths in decision diagrams related to the Haar wavelet transforms. In many cases, this reduction provides smaller size of such decision diagrams.