A Model for the Coanalysis of Hardware and Software Architectures

Authors:
Fred Rose;Todd Carpenter;Sanjaya Kumar;John Shackleton;Todd Steeves Honeywell
Affiliations:
Honeywell Technology Center, Minneapolis, MN;Honeywell Technology Center, Minneapolis, MN;Honeywell Technology Center, Minneapolis, MN;Honeywell Technology Center, Minneapolis, MN;Honeywell Technology Center, Minneapolis, MN
Venue:
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Year:
1996

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Abstract

Successful multiprocessor system design for complex real-time embedded applications requires powerful and comprehensive, yet cost-effective, productive, and maintain able modeling. The multi-disciplinary, VHDL-based modeling library developed by the Honeywell Technology Center places heavy emphasis on multiprocessing and distributed communications. These models focus on detailed hardware performance analysis along with multiple abstraction levels for software representation and evaluation. This paper will detail the processor model which provides the key element for the coanalysis of hardware and software system architectures.