SSIM: a software levelized compiled-code simulator
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Demand driven simulation: BACKSIM
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
LogP: towards a realistic model of parallel computation
PPOPP '93 Proceedings of the fourth ACM SIGPLAN symposium on Principles and practice of parallel programming
Partitioning of VLSI circuits and systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Functional simulation using binary decision diagrams
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Efficient circuit partitioning to extend cycle simulation beyond synchronous circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Graph partitioning models for parallel computing
Parallel Computing - Special issue on graph partioning and parallel computing
dibSIM: a parallel functional logic simulator allowing dynamic load balancing
Proceedings of the conference on Design, automation and test in Europe
The Designer's Guide to VHDL
The VERILOG Hardware Description Language
The VERILOG Hardware Description Language
Modular Construction of Model Partitioning Processes for Parallel Logic Simulation
ICPPW '01 Proceedings of the 2001 International Conference on Parallel Processing Workshops
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Cycle-based simulation at register-transfer- and gate level realized by a Levelized Compiled Code (LCC) technique represents a well established method for functional verification in processor design. Due to rapidly increasing design sizes, simulation acceleration is an important issue. We present a parallel LCC simulation system that has been developed to run on loosely-coupled systems. It comprises three parallel simulators and a complex model partitioning environment. An essential idea of our parallelization approach is to valuate circuit model partitions with respect to the expected parallel simulation run-time and to integrate corresponding cost functions into partitioning algorithms. This is done on the basis of a formal model of parallel LCC simulation. In this paper, we focus on the strong relation between model partitioning and the parallel simulation technique chosen. The components of the simulation system are outlined and experimental results with respect to simulation acceleration are given for IBM processor models of different size.