Hierarchical strategy of model partitioning for VLSI-design using an improved mixture of experts approach

  • Authors:
  • K. Hering;R. Haupt;Th. Villmann

  • Affiliations:
  • Universität Leipzig, Inst. für Informatik, Augustusplatz 10/11, 04109 Leipzig, Germany;Universität Leipzig, Inst. für Informatik, Augustusplatz 10/11, 04109 Leipzig, Germany;Inst. für Techno- und Wirtschaftsmathematik, E.-Schrödinger-Str., Geb. 48/575, 67663 Kaiserslautern , Germany

  • Venue:
  • PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
  • Year:
  • 1996

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Abstract

The partitioning of complex processor models on the gate and register-transfer level for parallel functional simulation based on the clock-cycle algorithm is considered. We introduce a hierarchical partitioning scheme combining various partitioning algorithms in the frame of a competing strategy. Melting together different partitioning results within one level using superpositions we crossover to a mixture of experts one. This approach is improved applying genetic algorithms. In addition we present two new partitioning algorithms both of them taking cones as fundamental units for building partitions.