Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Symbolic Model Checking
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
ACV: an arithmetic circuit verifier
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
PHDD: an efficient graph representation for floating point circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Bisimulation Minimization and Symbolic Model Checking
Formal Methods in System Design
Verifying the SRT Division Algorithm Using Theorem Proving Techniques
Formal Methods in System Design
Modular Verification of SRT Division
Formal Methods in System Design
Model Checking Large Software Specifications
IEEE Transactions on Software Engineering
Divider Circuit Verification with Model Checking and Theorem Proving
TPHOLs '00 Proceedings of the 13th International Conference on Theorem Proving in Higher Order Logics
A tutorial introduction to symbolic model checking
Logic for concurrency and synchronisation
Word-level sequential memory abstraction for model checking
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
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