A Method of Formal Verification of Cryptographic Circuits

  • Authors:
  • Kanji Hirabayashi

  • Affiliations:
  • Toshiba Research and Development Center, TTC, Komukai Toshiba-cho, Kawasaki, 210-0901, Japan. 000092010188@tg-mail.toshiba.co.jp

  • Venue:
  • Journal of Electronic Testing: Theory and Applications
  • Year:
  • 1998

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Abstract

A general method for determining whether a certain design is initializable, and for generating its initialization sequence, is presented in this paper. This method is based on structural decomposition of the circuit, and can handle both logical ...