An Algebraic Approach to Formal Verification of Microprocessors

Authors:
Kanji Hirabayashi
Affiliations:
Toshiba Techno Center Inc., Hamamatsucho 1-18-16, Tokyo 105-0013, Japan. kanji.hirabayashi@glb.toshiba.co.jp
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2001

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Abstract

In this letter we report the formal verification of microprocessors. After we describe algebraically a bit-sliced microprocessor at both function and logic levels, we apply the symbolic manipulation of Mathematica.