An Effective Built-In Self-Test Scheme for Parallel Multipliers
IEEE Transactions on Computers
A Fast Optimal Robust Path Delay Fault Testable Adder
EDTC '96 Proceedings of the 1996 European conference on Design and Test
(Quasi-) Linear Path Delay Fault Tests for Adders
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units
IEEE Transactions on Computers
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We present a performance driven generator for integer adders which has the following interesting feature: The generator is parametrized in the operands' bitlength n, the delay of the addition tn, and the fault model FM. FM may in particular be chosen as the classical stuck-at fault model, the cellular fault model or the robust path delay fault model. The output of the generator is a performance oriented conditional sum type adder, i.e., an area-minimal n-bit adder of the “conditional sum type” with delay ⩽tn (if it exists) together with a small complete test set with respect to the chosen fault model FM