Performance analysis of high speed hybrid CMOS full adder circuits for low voltage VLSI design

Authors:
Subodh Wairya;Rajendra Kumar Nagaria;Sudarshan Tiwari
Affiliations:
Department of Electronics Engineering, Institute of Engineering & Technology, Lucknow, India;Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad, India;Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad, India
Venue:
VLSI Design
Year:
2012

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Abstract

This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP), and energy delay product (EDP). Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits against the reported conventional adder circuits. The design is implemented on UMC0.18 µm process models in Cadence Virtuoso Schematic Composer at 1.8 V single-ended supply voltage, and simulations are carried out on Spectre S.