Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Performance analysis of low-power 1-Bit CMOS full adder cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Novel Low Power Energy Recovery Full Adder Cell
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Two new low-power Full Adders based on majority-not gates
Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel low-power full-adder cell for low voltage
Integration, the VLSI Journal
ULPFA: a new efficient design of a power-aware full adder
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A review of 0.18-µm full adder performances for tree structured arithmetic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and comparison on full adder block in submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Full adder is one of the most important digital components for which many improvements have been made to improve its architecture. In this paper, we present two new symmetric designs for Low-Power full adder cells featuring GDI (Gate-Diffusion Input) structure and hybrid CMOS logic style. The main design objectives for these adder modules are not only providing Low-Power dissipation and high speed but also full-voltage swing. In the first design, hybrid logic style is employed. The hybrid logic style utilizes different logic styles in order to create new full adders with desired performance. This provides the designer with a higher degree of design freedom to target a wide range of applications, hence reducing design efforts. The second design is based on a different new approach which eliminates the need of XOR/XNOR gates for designing full adder cell and also by utilizing GDI (Gate-Diffusion-Input) technique in its structure, it provides Ultra Low-Power and high speed digital component as well as a full voltage swing circuit. Many of the previously reported adders in literature suffered from the problems of low-swing and high noise when operated at low supply voltages. These two new designs successfully operate at low voltages with tremendous signal integrity and driving capability. In order to evaluate the performance of the two new full adders in a real environment, we incorporated two 16-bit ripple carry adders (RCA). The studied circuits are optimized for energy efficiency at 0.13@?m and 90nm PD SOI CMOS process technology. The comparison between these two novel circuits with standard full adder cells shows excessive improvement in terms of Power, Area, Delay and Power-Delay-Product (PDP).