Design of 9-transistor single bit full adder

Authors:
Manoj Kumar
Affiliations:
Guru Jambheshwar University of Science & Technology, Hisar, India
Venue:
Proceedings of the Second International Conference on Computational Science, Engineering and Information Technology
Year:
2012

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Abstract

Here, new low power single bit full adder using 9 transistors has been presented. The proposed adder has the advantage of low power consumption with less area requirements due fewer numbers of transistors. Low power goal has been achieved at circuit level by designing the adder with optimized XNOR gates and multiplexer approach. Direct path between supply voltage and ground have been minimized in the design. The circuits have been simulated in 0.18μm CMOS technology with SPICE. The adder shows power dissipation of 2.0773mW with maximum output delay of 1.86ps at supply voltage of 3.3V. Simulations have been carried out with varying supply voltage 3.3V to 2.7V. Power consumption of proposed full adder has been compared with earlier reported circuits and proposed circuit shows better results.