A survey of low power high speed one bit full adder

Authors:
N. M. Chore;R. N. Mandavgane
Affiliations:
Department of Electronic Engineering, B. D. College of Engineering, Rashtra Sant Tukdoji Maharaj Nagpur University, Wardha, Maharashtra, India;Department of Electronic Engineering, B. D. College of Engineering, Rashtra Sant Tukdoji Maharaj Nagpur University, Wardha, Maharashtra, India
Venue:
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
Year:
2010

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Abstract

In this paper, a structured approach for analyzing the adder design is introduced. Analysis is based on some simulation parameter like No. of transistors, power, delay, power delay product, different technologies, aspect ratio. Each reference used different tool for the simulation purpose. The different circuit design are studied and evaluated extensively. Several designs give a different designing approach and give a new information which can relate with different application. Each of these circuits cell exhibits different power consumption, delay and area in different VLSI technology. This paper can be said as a library of different full adder circuits that will be beneficial for the circuit designers to pick the full adder cell that satisfied their specific application.