Machine-learning-based circuit synthesis

Authors:
Lior Rokach;Meir Kalech;Gregory Provan;Alexander Feldman
Affiliations:
Ben Gurion University of the Negev, Be'er Sheva, Israel;Ben Gurion University of the Negev, Be'er Sheva, Israel;University College Cork, Cork, Ireland;University College Cork, Cork, Ireland
Venue:
IJCAI'13 Proceedings of the Twenty-Third international joint conference on Artificial Intelligence
Year:
2013

Citing 11
Cited 0

Absolute Minimization of Completely Specified Switching Functions

IEEE Transactions on Computers
Learning by discovering concept hierarchies

Artificial Intelligence
Logic Minimization Algorithms for VLSI Synthesis

Logic Minimization Algorithms for VLSI Synthesis
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering

IEEE Design & Test
A Genetic Programming Approach to Logic Function Synthesis by Means of Multiplexers

EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
Microarray data mining with visual programming

Bioinformatics
Automatic Synthesis of Combinational Logic Circuit with Gene Expression-Based Clonal Selection Algorithm

ICNC '08 Proceedings of the 2008 Fourth International Conference on Natural Computation - Volume 06
Use of automatically defined functions and architecture-altering operations in automated circuit synthesis with genetic programming

GECCO '96 Proceedings of the 1st annual conference on Genetic and evolutionary computation
Synthesis of boolean functions using information theory

ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Computer Arithmetic: Algorithms and Hardware Designs

Computer Arithmetic: Algorithms and Hardware Designs
Synthesis of P-circuits for logic restructuring

Integration, the VLSI Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

Multi-level logic synthesis is a problem of immense practical significance, and is a key to developing circuits that optimize a number of parameters, such as depth, energy dissipation, reliability, etc. The problem can be defined as the task of taking a collection of components from which one wants to synthesize a circuit that optimizes a particular objective function. This problem is computationally hard, and there are very few automated approaches for its solution. To solve this problem we propose an algorithm, called Circuit-Decomposition Engine (CDE), that is based on learning decision trees, and uses a greedy approach for function learning. We empirically demonstrate that CDE, when given a library of different component types, can learn the function of Disjunctive Normal Form (DNF) Boolean representations and synthesize circuit structure using the input library. We compare the structure of the synthesized circuits with that of well-known circuits using a range of circuit similarity metrics.