Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
IEEE Design & Test
Advanced Digital Design with the Verilog HDL
Advanced Digital Design with the Verilog HDL
Efficient resource utilization of FPGAs
Proceedings of the 7th International Conference on Frontiers of Information Technology
Hardware implementations of software programs based on hierarchical finite state machine models
Computers and Electrical Engineering
| Hi-index | 0.00 |
Field programmable gate arrays (FPGAs) are continuously gaining momentum and becoming essential part of today's digital systems and applications. The growing use of these devices coupled with increasingly more complex and integrated designs necessitates search for techniques in efficient utilization of their internal resources. Standard HDL coding techniques and synthesis tools implement logic to look up table (LUT) based architecture. The resulting design utilizes more area on the chip and some fast and dedicated areas and resources of the chip remain unutilized. This in turn results in slower clock rates and larger critical path lengths, hence the design remains inefficient in terms of both speed and area. In this paper we present and discuss techniques to effectively utilize the FPGA dedicated resources in order to speed up achievable clock rates and reduce the FPGA area utilization. Various useful HDL constructs are presented that utilize dedicated hardware resources of modern Xilinx FPGAs. Optimization techniques are presented with implementation examples and corresponding quantitative performance evaluation. In most of the cases we have achieved 50% reduction in chip area utilization and simultaneously improved timing results significantly.