Verilog HDL: a guide to digital design and synthesis
Verilog HDL: a guide to digital design and synthesis
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
IEEE Design & Test
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This paper considers the Alex language designed for describing digital circuits. This is a generalization of the nonbracket language notation ("Polish Notation") based on the deduction principle; i.e., an axiomatic theory has been constructed with a circuit notation being a theorem. We prove a metatheorem (theorem on the circuit notation) that sets necessary and sufficient conditions for a given sequence of symbols to be a theorem in this theory (i.e., a description of a circuit). The assumptions of this theorem can easily be verified and, therefore, used as means of syntactic control for the correctness of the circuit description. The description of circuits in the Alex language is optimal: the record length is equal to the number of links between the circuit elements. A specific feature of this language is that any subcircuit with a single output in the circuit record is depicted as a continuous segment of symbols. This feature makes it possible to easily perform equivalent transformations of the circuit on the basis of its record, by replacing some segments of symbols with other segments that are functionally equivalent. Some examples are provided to demonstrate the implementation of the algorithm of functional simulation of circuits described in Alex.