SubGemini: identifying subcircuits using a fast subgraph isomorphism algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
Signature hiding techniques for FPGA intellectual property protection
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Intellectual property protection by watermarking combinational logic synthesis solutions
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Robust FPGA intellectual property protection through multiple small watermarks
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Robust techniques for watermarking sequential circuit designs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Effective iterative techniques for fingerprinting design IP
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Behavioral synthesis techniques for intellectual property protection
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Forensic engineering techniques for VLSI CAD tools
Proceedings of the 37th Annual Design Automation Conference
Fingerprinting intellectual property using constraint-addition
Proceedings of the 37th Annual Design Automation Conference
Copy detection for intellectual property protection of VLSI designs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Publicly detectable techniques for the protection virtual components
Proceedings of the 38th annual Design Automation Conference
Modulation and Information Hiding in Images
Proceedings of the First International Workshop on Information Hiding
Performance Study of a Selective Encryption Scheme for the Security of Networked, Real-Time Video
ICCCN '95 Proceedings of the 4th International Conference on Computer Communications and Networks
Partial-encryption technique for intellectual property protection of FPGA-based products
IEEE Transactions on Consumer Electronics
Constraint-based watermarking techniques for design IP protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IPP@HDL: efficient intellectual property protection scheme for IP cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Secure public verification of IP marks in FPGA design through a zero-knowledge protocol
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RFID based access control protection scheme for SRAM FPGA IP cores
Microprocessors & Microsystems
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FPGAs, because of their re-programmability, are becoming very popular for creating and exchanging VLSI intellectual properties (IPs) in the reuse-based design paradigm. Existing watermarking and fingerprinting techniques successfully embed identification information into FPGA designs to deter IP infringement. However, such methods incur timing and/or resource overhead, unpredictable at times, which causes performance degradation. In this paper, we propose a new FPGA watermarking technique that guarantees zero design overhead.Our approach consists of two phases. First we design as usual to obtain the best, possible, quality IP. Then we map the required signature to additional timing constraints on carefully selected nets and redo a small portion of the design (e.g. place and route). The FPGA configuration bitstream for the resulting watermarked design will be significantly different from the original design, which provides us with a strong proof of authorship. The watermarking technique has zero design overhead because it is developed to maintain the performance of the design from the first phase. This is demonstrated by applying the proposed technique on several real-life FPGA designs, which range in size from a few thousand to more than two million gates, on Xilinx devices.