A secure scan design methodology
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Securing Designs against Scan-Based Side-Channel Attacks
IEEE Transactions on Dependable and Secure Computing
Scan Based Side Channel Attacks on Stream Ciphers and Their Counter-Measures
INDOCRYPT '08 Proceedings of the 9th International Conference on Cryptology in India: Progress in Cryptology
A new scan attack on RSA in presence of industrial countermeasures
COSADE'12 Proceedings of the Third international conference on Constructive Side-Channel Analysis and Secure Design
PUF-based secure test wrapper design for cryptographic SoC testing
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Designing secure ICs requires fulfilling many design rules in order to protect access to secret data. However, these security design requirements may be in opposition to test needs and testability improvement techniques that increase both observability and controllability. Nevertheless, secure chip designers cannot neglect the testability of their chip; a high quality production testing is primordial to ensure a good level of security since any faulty devices could induce major security vulnerability. In this paper, we propose to merge security requirements with testability ones in a control-oriented design for security scan technique.