Comparison of redundant architectures for two-step ADCs

  • Authors:

  • Gian Nicola Angotzi;Massimo Barbaro;Paul G.A. Jespers

  • Affiliations:

  • University of Cagliari, Cagliari, Italy;University of Cagliari, Cagliari, Italy;Université Catholique de Louvain, Louvain la Neuve, Belgium

  • Venue:
  • Proceedings of the 18th ACM Great Lakes symposium on VLSI
  • Year:
  • 2008

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Abstract

Redundancy in the output code, as instrument to reduce the impact of non-idealities in different architectures of two-step A to D converters, is investigated. A circuit model capable of providing an estimate of the required sizes for passive components for a given accuracy was developed. Such model represents an useful design tool, providing a way to calculate important figures of merit (area, power, ENOB, SNR, large-signal behavior) of the different ADCs. System-level simulation results are provided and discussed.