A transistor reordering technique for gate matrix layout

Authors:
Uminder Singh;C. Y. Roger Chen
Affiliations:
Department of Electrical and Computer Engineering, 121 Link Hall, Syracuse University, Syracuse, NY;Department of Electrical and Computer Engineering, 121 Link Hall, Syracuse University, Syracuse, NY
Venue:
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Year:
1991

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Abstract

An algorithm is introduced which uses logic equations to determine a gate sequence and a set of nets which optimize the gate matrix layout area. Using logic equations allows the reordering of transistors in a completely general manner. Previous works using net-lists and the concept of delayed binding performed only a small subset of the reordering possible with the proposed algorithm. The algorithm has a time complexity of &Ogr;(E log E) for a design with E equations. The experimental results show a considerable reduction in layout area.