Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Testing and error detection in iterative logic arrays
Testing and error detection in iterative logic arrays
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The testability of a class of circuits called generalized counters is investigated under a more powerful fault model than examined in earlier work. It is assumed that any number of full adders in a generalized counter can assume an incorrect function under fault, as long as the function remains combinational. The testability of the overall class of generalized counters is examined and it is shown that under a restricted fault model it is possible to detect all multiple faults with a test set that grows linearly with the number of counter inputs. It is then shown that for a subset of the class of generalized counters it is possible to detect multiple faults with a larger number of tests, linear to the number of counter inputs, when the restrictions on the fault model are relaxed.