The μVP 64-Bit Vector Coprocessor: A New Implementation of High-Performance Numerical Computation

Authors:
Makoto Awaga;Hiromasa Takahashi
Affiliations:
-;-
Venue:
IEEE Micro
Year:
1993

Citing 3
Cited 2

Computer architecture: a quantitative approach

Computer architecture: a quantitative approach
Computer Arithmetic: Principles, Architecture and Design

Computer Arithmetic: Principles, Architecture and Design
The Architecture of Symbolic Computers

The Architecture of Symbolic Computers

A highly efficient implementation of back propagation algorithm using matrix instruction set architecture

Neural, Parallel & Scientific Computations
A highly efficient implementation of a backpropagation learning algorithm using matrix ISA

Journal of Parallel and Distributed Computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

The architecture and design of the 驴VP, a single-chip vector coprocessor developed to meet the needs of high-performance processors, are described. The 驴VP is a supercomputer component implemented on a single large-scale-integrated (LSI) CMOS chip. With 206 MFLOPS single-precision and 106-MFLOPS double-precision performance at 50 MHz, the 驴VP offers a rate almost equivalent to that typical minisupercomputers.