Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis

Authors:
Makoto Motegi;Naofumi Homma;Takafumi Aoki;Tatsuo Higuchi
Affiliations:
-;-;-;-
Venue:
PPSN VII Proceedings of the 7th International Conference on Parallel Problem Solving from Nature
Year:
2002

Citing 4
Cited 0

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Abstract

This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the design of bit-serial arithmetic circuits, which frequently appear in real-time DSP architectures. The potential of the proposed approach is examined through experimental synthesis of bit-serial constant-coefficient multipliers. A new version of the EGG system can generate the optimal bit-serial multipliers of 8-bit coefficients with a 100% success rate in 15 minutes on an average.