A single chip, pipelined, cascadable, multichannel, signal processor

  • Authors:

  • S. Krishnakumar;P. Suresh;S. Sadashiva Rao;M. P. Pareek;R. Gupta

  • Affiliations:

  • -;-;-;-;-

  • Venue:
  • VLSID '95 Proceedings of the 8th International Conference on VLSI Design
  • Year:
  • 1995

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Abstract

The architectures of general purpose digital signal processors fail to deliver acceptable performance for multichannel signal processing. This paper describes a 40K transistor execution unit that is optimised for the processing of multichannel signals. The signal processor incorporates two 12 bit array multipliers and a 128 deep programmable delay line. To facilitate the programming of the device, it is designed to function as a memory mapped peripheral to a 16/32 bit microprocessor. It supports online diagnostics through the incorporation of shadow accumulators. It is fabricated in SCL's 2/spl mu/m double metal CMOS process and packaged in a 144 pin CPGA.