Design and VLSI implementation of a novel concurrent 16-bit multiplier-accumulator for DSP applications

• Authors: D. V. Poornaiah;R. Haribabu;M. O. Ahmad
• Venue: ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: plenary, special, audio, underwater acoustics, VLSI, neural networks - Volume I
• Year: 1993

In this paper, we propose an efficient carry-save algorithm based on Baugh-Wooley transformation technique and map it onto a novel concurrent multiplier-accumulator (CMAC) architecture that can be configured on-the-fly for selecting multiply alone or multiply-add/subtract computations involving unsigned/signed 2's compliment/mixed-mode data formats. The proposed CMAC does not require the use of a separate adder module thereby achieving a reduction of 50% in the computation time along with 20% savings in the area when compared with the conventional MACs. The CMAC, while, maintaining functional as well as near total pin compatibility with the industry standard MACs, such as, ADSP1010 and TDC 1010 series provides additional features of mixed-mode data format, saturation arithmetic logic and on-chip test logic for the measurement of the critical path delay. A 16×16 CMAC based on carry-save and carry look-ahead techniques is designed and extensively simulated with a cycle time of 80 ms using the 1-micron CMOS gate array technology rules of VLSI Technology Inc. This chip is currently laid-out in 68-pin PLCC package.