A simulation based study of TLB performance
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Reducing TLB power requirements
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Skew-tolerant circuit design
Managing leakage for transient data: decay and quasi-static 4T memory cells
Proceedings of the 2002 international symposium on Low power electronics and design
TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors
Proceedings of the 2002 international symposium on Low power electronics and design
Compiler-directed code restructuring for reducing data TLB energy
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An energy efficient TLB design methodology
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
High performance set associative translation lookaside buffers for low power microprocessors
Integration, the VLSI Journal
Optimizing CAM-based instruction cache designs for low-power embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
B2P2: bounds based procedure placement for instruction TLB power reduction in embedded systems
Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems
Energy-Effective instruction fetch unit for wide issue processors
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
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Lowering active power dissipation is increasingly important for battery powered embedded microprocessors. Here, power reduction techniques applicable to fully associative translation lookaside buffers, as well as other associative structures and dynamic register files, are described. Powermill simulations of implementation in a microprocessor on 0.18mm process technology demonstrate 42% power savings. Circuit implementations, as well as architectural simulations demonstrating applicability to typical instruction mixes are shown.