Analysis and design of low-energy flip-flops
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
A 225 MHz resonant clocked ASIC chip
Proceedings of the 2003 international symposium on Low power electronics and design
Energy recovery clocking scheme and flip-flops for ultra low-energy applications
Proceedings of the 2003 international symposium on Low power electronics and design
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication
Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication
| Hi-index | 0.00 |
Eleven latch circuits for ultra-low-power applications with resonant clocking are compared in terms of energy dissipation (the main focus of this work), propagation delay, set-up, and hold time in a wide range of operating frequencies and supply voltages. Transistor-level simulations in a 0.18 µm process point out that the ratioless circuit Cut Cross-over current latch (CC-Latch) saves up to 15% energy towards the second best competitor in low- to mid-frequency applications. The improved efficiency is due to the suppression of the excess of cross-over current, by switching of the pull-up or the pull-down network alternatively in the forward inverter of the latch.