Analysis of Gate Oxide Shorts in CMOS Circuits
IEEE Transactions on Computers
A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors
Journal of Electronic Testing: Theory and Applications
A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Boolean and Current Detection of MOS Transistor with Gate Oxide Short
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Encountering gate oxide breakdown with shadow transistors to increase reliability
Proceedings of the 21st annual symposium on Integrated circuits and system design
Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
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This paper presents a new model for gate-to-channel GOS defects. The transistors used in digital cell library are usually designed with a minimum-size. This new model permits to handle minimal-length transistors allowing the simulation of GOS defects in realistic digital circuits. Based on the electrical analysis of the defect behavior, a comprehensive method for the model construction is detailed. It is shown that the behavior of the proposed model matches in a satisfactory way the behavior of a defective transistor including the random parameters of the defect.