The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
On accuracy of switch-level modeling of bridging faults in complex gates
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Transistor-level test generation for physical failures in CMOS circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
"Resistive Shorts" Within CMOS Gates
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Toward understanding "Iddq-only" fails
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Boolean and Current Detection of MOS Transistor with Gate Oxide Short
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short
Journal of Electronic Testing: Theory and Applications
A compact DC model of gate Oxide short defect
Microelectronic Engineering - Special issue: Proceedings of the 13th biennial conference on insulating films on semiconductors
Testing CMOS logic gates for realistic shorts
ITC'94 Proceedings of the 1994 international conference on Test
| Hi-index | 14.98 |
The resistance dependence, voltage dependence, temperature dependence, and pattern dependence properties of CMOS logic gate operation in the presence of gate oxide shorts are analyzed. The analysis is based on realistic defect models that incorporate the resistive nature of gate oxide shorts and the difference between gate oxide shorts in n- and p-channel transistors.