A compact DC model of gate Oxide short defect

Authors:
R. Bouchakour;J. M. Portal;J. M. Gallière;F. Azais;Y. Bertrand;M. Renovell
Affiliations:
L2MP, UMR CNRS 6137, IMT Technopole de Chateau Gombert, 13451 Marseille cedex 20, France;L2MP, UMR CNRS 6137, IMT Technopole de Chateau Gombert, 13451 Marseille cedex 20, France;LIRMM, UMII, 161 rue Ada, 34392 Montpellier, France;LIRMM, UMII, 161 rue Ada, 34392 Montpellier, France;LIRMM, UMII, 161 rue Ada, 34392 Montpellier, France;LIRMM, UMII, 161 rue Ada, 34392 Montpellier, France
Venue:
Microelectronic Engineering - Special issue: Proceedings of the 13th biennial conference on insulating films on semiconductors
Year:
2004

Citing 6
Cited 0

Analysis of Gate Oxide Shorts in CMOS Circuits

IEEE Transactions on Computers
A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors

Journal of Electronic Testing: Theory and Applications
Boolean and current detection of MOS transistor with gate oxide short

Proceedings of the IEEE International Test Conference 2001
A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level

Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS

Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Operation and Modeling of the Mos Transistor (The Oxford Series in Electrical and Computer Engineering)

Operation and Modeling of the Mos Transistor (The Oxford Series in Electrical and Computer Engineering)

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper a new electrical transistor compact model including a gate oxide short defects is proposed based on a charge sheet model approach. The basic equations and the topology of the model are presented in detail. It is demonstrated that the electrical behaviour of the proposed model matches in a satisfactory way the defective transistor behaviour.