Enhancing Yield at the End of the Technology Roadmap
IEEE Design & Test
Yield analysis for self-repairable MEMS devices
Analog Integrated Circuits and Signal Processing
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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A topic of great concern in VSLI manufacture is yield. One way to improve practical yield is to design redundant memory or logic circuits and switch over to this redundant circuit if fault occurs in the principle memory or main logic circuit.This paper reports the repairing ratio of no good devices on the main circuit and how large of a redundancy-repairing circuit would be economically feasible.