Identifying loops using DJ graphs
ACM Transactions on Programming Languages and Systems (TOPLAS)
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Partitioned instruction cache architecture for energy efficiency
ACM Transactions on Embedded Computing Systems (TECS)
Testing flow graph reducibility
STOC '73 Proceedings of the fifth annual ACM symposium on Theory of computing
A highly configurable cache for low energy embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Custom Instruction Filter Cache Synthesis for Low-Power Embedded Systems
RSP '05 Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping
Profile Directed Instruction Cache Tuning for Embedded Systems
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
The M5 Simulator: Modeling Networked Systems
IEEE Micro
Rapid estimation of instruction cache hit rates using loop profiling
ASAP '08 Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors
| Hi-index | 0.00 |
Cache tuning has been shown to achieve considerable energy savings and methods have also been proposed for tuning the cache for standalone embedded applications. However, with the increasing complexity of modern day embedded applications, RTOS based multitasking systems are fast becoming the norm. Therefore, there exists a need for techniques to tune the cache for multitasking systems. In this paper we present a framework for energy centric tuning of the instruction cache for embedded multitasking systems. Our framework is built upon a formal model for characterizing multitasking systems and is suitable for fast instruction cache tuning using loop profiling. We validate our proposed techniques by applying them to tune a predictor based filter cache hierarchy - a common solution for low power embedded systems. For all the multitasking programs tested, our techniques are able to successfully predict configurations that are optimal or near-optimal. The proposed methods are also able to achieve speed-ups of up to an order of magnitude compared to exhaustive design space exploration techniques.