Instruction Cache Tuning for Embedded Multitasking Applications
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
A survey on cache tuning from a power/energy perspective
ACM Computing Surveys (CSUR)
Hi-index | 0.00 |
Cache memories improve the performance due to the locality found within the loops of application. Because these loop characteristics are application dependent, the optimal cache hierarchy for performance and energy saving is also application dependent. Traditionally, cache simulations are employed to tune the cache hierarchy. In this paper we propose a simple yet effective loop profiler directed methodology for instruction cache hierarchy optimization. The proposed methodology utilizes the loop characteristics of the application which are readily available from the compiler making it easy to adopt the methodology in an existing design flow.