An FPGA-based scalable simulation accelerator for tile architectures

  • Authors:

  • Shinya Takamaeda-Yamazaki;Ryosuke Sasakawa;Yoshito Sakaguchi;Kenji Kise

  • Affiliations:

  • Graduate School of Information Science and Engineering, Tokyo Institute of Technology and JSPS Research Fellow;Graduate School of Information Science and Engineering, Tokyo Institute of Technology;Graduate School of Information Science and Engineering, Tokyo Institute of Technology;Graduate School of Information Science and Engineering, Tokyo Institute of Technology

  • Venue:
  • ACM SIGARCH Computer Architecture News
  • Year:
  • 2011

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Abstract

FPGA-based simulation systems can simulate processor behavior in realistic time. In order to practically simulate tile many-core architectures, we propose ScalableCore for prototyping system development using multiple FPGAs. In this paper, we present an FPGA-based platform called ScalableCore system 1.1, which consists of several simulation tiles named ScalableCore Units. Each tile is connected to four neighbor tiles via interface boards called ScalableCore Boards, and so increasing the target number of cores is easy. We also describe useful techniques by which to achieve high scalability of simulation and to implement complicated hardware functions on an FPGA. The developed system simulates the behavior of a tile architecture with DMA communications and NoC 14.2 times faster than a corresponding software-based functional simulator running on a standard computer with an Intel Core2Duo processor. We verified that the ScalableCore system is cycle-accurate by comparing the simulation behavior on a software-based simulator.