ScalableCore system: a scalable many-core simulator by employing over 100 FPGAs

Authors:
Shinya Takamaeda-Yamazaki;Shintaro Sano;Yoshito Sakaguchi;Naoki Fujieda;Kenji Kise
Affiliations:
Graduate School of Information Science and Engineering, Tokyo Institute of Technology, Tokyo, Japan and JSPS Research Fellow, Japan;Graduate School of Information Science and Engineering, Tokyo Institute of Technology, Tokyo, Japan;Graduate School of Information Science and Engineering, Tokyo Institute of Technology, Tokyo, Japan;Graduate School of Information Science and Engineering, Tokyo Institute of Technology, Tokyo, Japan;Graduate School of Information Science and Engineering, Tokyo Institute of Technology, Tokyo, Japan
Venue:
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Year:
2012

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Abstract

FPGA-based processor prototyping system can fast simulate processor behavior and enables longer time simulations to obtain useful evaluation information. In this paper we present ScalableCore system 3.3, which is an FPGA-based simulator of NoC-based tile architectures by employing multiple Xilinx Spartan-6 FPGAs. Two key techniques enable the system to achieve scalable speed of simulations by using corresponding amount of FPGAs to the target number of processor cores. We evaluated behavior of a processor consisting of 100 cores and a mesh NoC by using our developed system. The simulation speed is 129 times faster than the one of a software-based simulator running on a standard computer of Core i7 processor.