A Study of an Infrastructure for Research and Development of Many-Core Processors

Authors:
Koh Uehara;Shimpei Sato;Takefumi Miyoshi;Kenji Kise
Affiliations:
-;-;-;-
Venue:
PDCAT '09 Proceedings of the 2009 International Conference on Parallel and Distributed Computing, Applications and Technologies
Year:
2009

Citing 0
Cited 2

An FPGA-based scalable simulation accelerator for tile architectures

ACM SIGARCH Computer Architecture News
ScalableCore system: a scalable many-core simulator by employing over 100 FPGAs

ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

Many-core processors which have thousands of cores on a chip will be realized. We developed an infrastructure which accelerates the research and development of such many-core processors. This paper describes three main elements provided by our infrastructure. The first element is the definition of simple many-core processor architecture called M-Core. The second is SimMc, a software simulator of M-Core. The third is the software library MClib which helps the development of application programs for M-Core. The simulation speed of SimMc and the parallelization efficiency of M-Core are evaluated using some benchmark programs. We show that our infrastructure accelerates the research and development of many-core processors.