High-endurance hybrid cache design in CMP architecture with cache partitioning and access-aware policy

Authors:
Shun-Ming Syu;Yu-Hui Shao;Ing-Chao Lin
Affiliations:
National Cheng Kung University, Tainan, Taiwan Roc;National Cheng Kung University, Tainan, Taiwan Roc;National Cheng Kung University, Tainan, Taiwan Roc
Venue:
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Year:
2013

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Abstract

In recent years, NVM (non-volatile memory) technologies, such as STT-RAM (spin transfer torque RAM) and PRAM (phase change RAM), have drawn a lot of attention due to their low leakage and high density. However, both NVMs suffer from high write latency and limited endurance problems. To overcome these problems, the SRAM/NVM hybrid cache architecture has been proposed, and the write pressure on NVM can be mitigated with appropriate write management policy. Moreover, many wear leveling techniques have been proposed to extend the lifetime of NVM in the hybrid cache. In this paper, we proposed a hybrid cache design that includes SRAM cache, STT-RAM cache, and STT-RAM/SRAM hybrid cache banks for CMP (chip multi-processors) architecture. We also propose a partition-level wear leveling scheme and access-aware policies to mitigate unbalanced wear-out of STT-RAM lines within a partition and among different cache partitions. Experimental results show that, our proposed scheme and policies can achieve an average of 89 times improvement in cache lifetime and are able to save 58% power consumption compared to SRAM cache.