The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The case for a single-chip multiprocessor
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Proceedings of the 27th annual international symposium on Computer architecture
Memory Controller Optimizations for Web Servers
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
A Performance Comparison of DRAM Memory System Optimizations for SMT Processors
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
The M5 Simulator: Modeling Networked Systems
IEEE Micro
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Memory Access Scheduling Schemes for Systems with Multi-Core Processors
ICPP '08 Proceedings of the 2008 37th International Conference on Parallel Processing
Core-aware memory access scheduling schemes
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
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In Chip multiprocessor (CMP) systems, DRAM memory is a critical resource shared among cores Scheduled by one single memory controller, memory access requests from different cores may interfere with each other This interference causes extra waiting time for threads and leads to negligible overall system performance loss In conventional thread-unaware memory scheduling patterns, different threads probably experience extremely different performance; one thread is starving severely while another is continuously served Therefore, fairness should also be considered besides data throughput in CMP memory access scheduling to maintain the overall system performance This paper proposes a Fair Thread-Aware Memory scheduling algorithm (FTAM) that ensures both the fairness and memory system performance FTAM algorithm schedules requests from different threads by considering multiple factors, including the source thread information, the arriving time and the serving history of each thread As such FTAM considers the memory characteristic of each thread while maintains a good fairness among threads to avoid performance loss Simulation shows that FTAM significantly improves the system fairness by decreasing the unfairness index from 0.39 to 0.08 without sacrificing data throughput compared with conventional scheduling algorithm.