Reconfigurable Multicore Server Processors for Low Power Operation

  • Authors:
  • Ronald G. Dreslinski;David Fick;David Blaauw;Dennis Sylvester;Trevor Mudge

  • Affiliations:
  • Advanced Computer Architecture Labratory, University of Michigan, Ann Arbor 48109;Advanced Computer Architecture Labratory, University of Michigan, Ann Arbor 48109;Advanced Computer Architecture Labratory, University of Michigan, Ann Arbor 48109;Advanced Computer Architecture Labratory, University of Michigan, Ann Arbor 48109;Advanced Computer Architecture Labratory, University of Michigan, Ann Arbor 48109

  • Venue:
  • SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
  • Year:
  • 2009

Quantified Score

Hi-index 0.00

Visualization

Abstract

With power becoming a key design constraint, particularly in server machines, emerging architectures need to leverage reconfigurable techniques to provide an energy optimal system. The need for a single chip solution to fit all needs in a warehouse sized server is important for designers. This allows for simpler design, ease of programmability, and part reuse in all segments of the server. A reconfigurable design would allow a single chip to operate efficiently in all aspects of a server providing both single thread performance for tasks requiring it, and efficient parallel processing helping to reduce power consumption. In this paper we explore the possibility of a reconfigurable server part and discuss the benefits and open questions still surrounding these techniques.