Communications of the ACM
Adding Limited Reconfigurability to Superscalar Processors
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques
A chip prototyping substrate: the flexible architecture for simulation and testing (FAST)
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Dynamically managed multithreaded reconfigurable architectures for chip multiprocessors
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Path-based scheduling in a hardware compiler
Proceedings of the Conference on Design, Automation and Test in Europe
ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Shared reconfigurable fabric for multi-core customization
Proceedings of the 48th Design Automation Conference
Online scheduling for multi-core shared reconfigurable fabric
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Hybrid compile and run-time memory management for a 3D-stacked reconfigurable accelerator
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
| Hi-index | 0.00 |
The shift to multi-core processors presents a number of opportunities and challenges to different research fields, including the field of FPGA applications. This paper investigates the advantages of combining multi-core processors and reconfigurable instruction set extensions. Both our analysis and the experimental results show that these two approaches exploit different levels of parallelism. Using a case study on the Floyd-Warshall algorithm, we demonstrate that the multi-core architecture and the reconfigurable instruction set extensions complement each other. By combining these two methods together we find a win-win solution, which gives us a more efficient implementation with higher performance.