An Enhanced HyperTransport Controller with Cache Coherence Support for Multiple-CMP

Authors:
Huandong Wang;Dan Tang;Xiang Gao;Yunji Chen
Affiliations:
-;-;-;-
Venue:
NAS '09 Proceedings of the 2009 IEEE International Conference on Networking, Architecture, and Storage
Year:
2009

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A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only)

Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays

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Abstract

HyperTransport link is a high performance IO interface for system connection. In this paper, the architecture of a HyperTransport interface is introduced.This HyperTransport interface realizes efficient HT-AXI bidirectional transformation, where AXI is a popular bus protocol in SOC architectures. Furthermore, this HyperTransport interface provides dedicated hardware support for cache coherence protocol. Through this HyperTransport interface, Godson-3A multi-core processor chips can be interconnected together to forma 4-16 core CC-NUMA system or a large-scale NCCNUMA system. The verification of the HyperTransport interface is also presented.