Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
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A comprehensive guidebook, ARM Synthesizable Designs with Actel FPGAs features: Verilog HDL Synthesis and SimulationActel IGLOO for Low Power, Fusion for Mixed Signal, and ProASIC3 for Performance ApplicationsFlash Lock Technology for data secure designs and instant on Flash CMOS technologyARM CortexM1 and ARM7S/MP7 enabled FPGA design with royalty-free IPState of the art SoC EDA synthesis and simulation toolsActel, Mentor Graphics, and Synopsys free one-year FPGA design tool licensesActel DVDROM: Libero FPGA design tools for ARM CortexM1 & ARM7TDMIARM DVDROM: ARM developers reference manuals and tools Table of contentsModule-section 1: HDL ( Verilog hardware description language) Simulation and Synthesis and FPGA basic logic configuration. Ch 1 Review of Synthesizable Verilog HDL (hardware description language)Ch 2 Simulation, regression and Formal verification of Verilog HDL (hardware description language) digital designs. Ch 3 ModelSim, Precision and Synplify Pro Simulation and Synthesis EDA (Electronic Design Automation) tools for digital design. Ch 4 Actel FPGA architectures, benefits, granularity, logic gate mapping equivalency, I/O, clocking, PLL and DDR options.Ch 5 Actel Libero design flow introduction for Reconfigurable EE/Flash based PASIC3 and Fusion technology. Module 2 ARM*/Cortex ISA (instruction set architecture), IP (intellectual property) library and RTL structure. Ch 6 ARM* ISA (instruction set architecture) instruction pipelinesCh 7 ARM*/AMBA buss architecture describing registers, datapath, co-processor and SoC memory options Ch 8 ARM/AMBA peripherals and IP (intellectual property) library Ch 9 MP7-ARM7 SoC HDL (hardware description language) example built on the Actel Fusion device. Module 3: IP (intellectual property) library, Synthesizing, Place and Routing a peripheral, then hierarchically a SoC. Ch 10 FIFO and I/O HDL (hardware description language) to gates examples. Ch 11 DDR (double data rate) HDL (hardware description language) to gates example. Ch 12 MP7 SoC HDL (hardware description language) to gates example with 10 ARM7 peripherals. Complete a h/w architecture HDL (hardware description language) design cycle. Module 4: Programming the MP7/ARM7 with user applications.Ch 13. ARM-KEIL Real View and GNU tools environment for user software applications development. Assembly and C programming examples Ch 14 ARM7/MP7 SoC HVAC application examples. Complete a software design modification cycle. Module 5: AppendicesCh 15 A: Modelsim user manualCh 16 B. Precision user manualCh 17 C. Synplify Pro user manualCh 18 D. Libero user manualCh 19 E. Stanford University Raksha project using a modified SPARC Leon3 Verilog HDL and implemented on a Xilinx XUP Board. Ch 20 F. Fusion Development System with options Ch 21 G. Actel University Board user manual