First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Variational delay metrics for interconnect timing analysis
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Modeling the Driver Load in the Presence of Process Variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
As CMOS technology enters the nanometer regime, the increasing process variation is bringing manifest impact on circuit performance. To accurately take account of both global and local process variations, a large number of random variables (or parameters) have to be incorporated into circuit models. This measure in turn raises the complexity of the circuit models. The current paper proposes a Principle Hessian Direction (PHD) based parameter reduction approach for interconnect networks. The proposed approach relies on each parameter's impact on circuit performance to decide whether keeping or reducing the parameter. Compared with existing principle component analysis(PCA) method, this performance based property provides us a significantly smaller parameter set after reduction. The experimental results also support our conclusions. In interconnect cases, the proposed method reduces 70% of parameters. In some cases (the mesh example in the current paper), the new approach leads to an 85% reduction. We also tested ISCAS benchmarks. In all cases, an average of 53% of reductionis observed with less than 3% error in mean and less than 8% error in variation.