TAU 2013 variation aware timing analysis contest

Authors:
Debjit Sinha;Luis Guerra e Silva;Jia Wang;Shesha Raghunathan;Dileep Netrabile;Ahmed Shebaita
Affiliations:
IBM Systems and Technology Group, Hopewell Junction, New York, USA;INESC-ID / IST - TU, Lisbon, Portugal;Illinois Institute of Technology, Chicago, Illinois, USA;IBM Systems and Technoloy Group, Bangalore, India;IBM Systems and Technology Group, Burlington, Vermont, USA;Synopsys, Sunnyvale, California, USA
Venue:
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Year:
2013

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Abstract

Timing analysis is a key component of any integrated circuit (IC) chip design-closure flow, and is employed at various stages of the flow including pre/post-route timing optimization and timing signoff. While accurate timing analysis is important, the run-time of the analysis is equally critical with growing chip design sizes and complexity (for example, increasing number of clocks domains, voltage islands, etc.). In addition, the increasing significance of variability in the chip manufacturing process as well as environmental variability necessitates use of variation aware techniques (e.g. statistical, multi-corner) for chip timing analysis which significantly impacts the analysis run-time. The aim of the TAU 2013 variation aware timing contest is to seek novel ideas for fast variation aware timing analysis, by means of the following: (a) increase awareness of variation aware timing analysis and provide insight into some challenging aspects of the analysis, (b) encourage novel parallelization techniques (including multi-threading) for timing analysis, and (c) facilitate creation of a publicly available variation aware timing analysis framework and benchmarks to further advance research in this area.