Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications

  • Authors:

  • Satoshi Komatsu;Masahiro Fujita

  • Affiliations:

  • The authors are with the VLSI Design and Education Center, The University of Tokyo, Tokyo, 113-0032 Japan. E-mail: komatsu@cad.t.u-tokyo.ac.jp, E-mail: fujita@ee.t.u-tokyo.ac.jp;The authors are with the VLSI Design and Education Center, The University of Tokyo, Tokyo, 113-0032 Japan. E-mail: komatsu@cad.t.u-tokyo.ac.jp, E-mail: fujita@ee.t.u-tokyo.ac.jp

  • Venue:
  • IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
  • Year:
  • 2005

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Abstract

Energy consumption is one of the most critical constraints in the current VLSI system designs. In addition, fault tolerance of VLSI systems will be also one of the most important requirements in the future shrunk VLSIs. This paper proposes practical low power and fault tolerant bus encoding methods in on-chip data transfer. The proposed encoding methods use the combination of simple low power code and fault tolerant code. Experimental results show that the proposed methods can reduce signal transitions by 23% on the bus with fault tolerance. In addition, circuit implementation results with bus signal swing optimization show the effectiveness of the proposed encoding methods. We show also the selection methodology of the optimum encoding method under the given requirements.