Delay aware, reconfigurable security for embedded systems
Proceedings of the ICST 2nd international conference on Body area networks
Optimal dual voltage assignment algorithm for low power under timing-constraints
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
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Reduction in power consumption has been an important concern in low-power and high-performance systems. This paper addresses the problem of static voltage scaling in such systems which is a well studied technique. In this paper we present an optimal methodology for static voltage scaling. Previous techniques, use path-based timing constraints in the system model which requires exponential runtime even for problem generation. Our main contribution is the unified formulation with linear number of constraints in the optimization problem as opposed to the exponential number. This methodology results in a fully polynomial time solvable problem.Our formulation can be applied to dynamic voltage scaling on single or multiple resources and moreover, it results in a convex optimization problem which can be solved in fully polynomial time. We propose a general formulation for bounded supply voltage assignments as well. Furthermore, we present two heuristics to find and/or map optimal voltages to discrete levels. We evaluated the performance of our techniques on benchmarks from TGFF and MPEG4 video encoder. An average of 43.96% power reduction was gained for unbounded supply voltage assignment along with40% average power saving where discrete voltage levels are available.