Differential static ultra low-voltage CMOS flip-flop for high speed applications

Authors:
Yngvar Berg
Affiliations:
Vesfold University College, Institute for Microsystems Technology, Horten, Norway
Venue:
CSECS'11/MECHANICS'11 Proceedings of the 10th WSEAS international conference on Circuits, Systems, Electronics, Control & Signal Processing, and Proceedings of the 7th WSEAS international conference on Applied and Theoretical Mechanics
Year:
2011

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Abstract

In this paper we present a simple ultra low-voltage and high speed D flip-flop. The delay of the static differential flip-flop presented is less than 12% compared to conventional differential CMOS flip-flops. The presented circuits have been simulated using Hspice and are valid for 90nm TSMC CMOS process. The proposed high-speed and ultra low-voltage flip-flop can be used for any digital low-voltage CMOS application.