High Speed Ultra Low Voltage CMOS inverter

Authors:
Yngvar Berg;Omid Mirmotahari;Johannes Goplen Lomsdalen;Snorre Aunet
Affiliations:
-;-;-;-
Venue:
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Year:
2008

Citing 0
Cited 2

Differential static ultra low-voltage CMOS flip-flop for high speed applications

CSECS'11/MECHANICS'11 Proceedings of the 10th WSEAS international conference on Circuits, Systems, Electronics, Control & Signal Processing, and Proceedings of the 7th WSEAS international conference on Applied and Theoretical Mechanics
Static ultra low-voltage and high performance CMOS NAND and NOR gates

CSECS'11/MECHANICS'11 Proceedings of the 10th WSEAS international conference on Circuits, Systems, Electronics, Control & Signal Processing, and Proceedings of the 7th WSEAS international conference on Applied and Theoretical Mechanics

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper we discuss timing details and performance of the ultra low voltage (ULV) logic style [3]. The ULV logic gates can be utilized to design high speed systems operating at ultra low supply voltages. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offsets voltages are used to shift the effective threshold voltage of the evaluating transistors. The simulated data presented is obtained using the Spectre simulator provided by Cadence and valid for a 90nm CMOS process.