Highly accurate data value prediction using hybrid predictors
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Predictive techniques for aggressive load speculation
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Timing Models for MOS Circuits
Timing Models for MOS Circuits
A static and dynamic energy reduction technique for I-cache and BTB in embedded processors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A leakage-energy-reduction technique for highly-associative caches in embedded systems
MEDEA '03 Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture
A cache design for high performance embedded systems
Journal of Embedded Computing - Cache exploitation in embedded systems
Reducing non-deterministic loads in low-power caches via early cache set resolution
Microprocessors & Microsystems
A leakage-energy-reduction technique for cache memories in embedded processors
Journal of Embedded Computing - Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications
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It has become an important requirement to achieve high performance and low-power consumption at the same time. The dynamic leakage cut-off (DLC) scheme, which controls transistors' threshold voltage by the line on demand, is a technique that potentially satisfies that requirement for a cache. Yet, conventional DLC causes access time to significantly lengthen, and consequently processor performance is unacceptably degraded. This paper proposes a mechanism that suppresses the performance degradation by preactivating cache lines using address prediction before access requests. Our evaluation results show significant performance improvements are achieved with little increase of power consumption.