The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Pipeline gating: speculation control for energy reduction
Proceedings of the 25th annual international symposium on Computer architecture
A low power SRAM using auto-backgate-controlled MT-CMOS
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Power aware microarchitecture resource scaling
Proceedings of the conference on Design, automation and test in Europe
A system level memory power optimization technique using multiple supply and threshold voltages
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
A preactivating mechanism for a VT-CMOS cache using address prediction
Proceedings of the 2002 international symposium on Low power electronics and design
Power-Driven Challenges in Nanometer Design
IEEE Design & Test
Design Challenges of Technology Scaling
IEEE Micro
An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Static energy reduction techniques for microprocessor caches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Thrifty BTB: A comprehensive solution for dynamic power reduction in branch target buffers
Microprocessors & Microsystems
| Hi-index | 0.00 |
Power consumption is becoming one of the most important constraints for embedded processor design in nano-meter-scale technologies. Especially, as the transistor supply voltage and threshold voltage are scaled down, leakage energy consumption is increased even when the transistor is not switching. This paper proposes to use the loop cache to reduce static energy consumption as well as dynamic one. We combine it with CMOS circuits having sleep mode, and thus instruction cache can go to sleep mode when the loop cache is active. Detailed simulation shows that we can reduce static energy consumed by I-cache by up to 37.9%. We also propose to apply the technique to branch target buffer, and its static and dynamic energy consumption is reduced by up to 40.4% and 40.7%, respectively.